
129
8024A–AVR–04/08
ATmega8HVA/16HVA
Notes:
2. Initial value: SCPT[0x10](1ms).
3. An additional delay T
d can be expected after enabling the Discharge FET due to initialization of
the protection circuit. With nomial ULP frequency this delay is maximum 86 s.
Note:
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPSCTR register is written. Any
writing to the BPSCTR register during this period will be ignored.
23.9.4
BPOCTR – Battery Protection Over-current Timing Register
Bit 7:6 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bit 5:0 – OCPT5:0: Over-current Protection Timing
These bits control the delay of the Over-circuit Protection. The Over-current Timing can be set
Notes:
2. Initial value.
3. An additional delay Td can be expected after enabling the corresponding FET. This is related to
the initialization of the protection circuitry. For the Discharge Over-Current protection, this
...
0x7E
(7.83 - 7.88 ms) + T
0x7F
Table 23-2.
Short-circuit Protection Reaction Time. SCPT[6:0] with corresponding Short-cir-
cuit Delay Time.
Short-circuit Protection Reaction Time(1)
Bit
765
4321
0
–
OCPT[5:0]
BPOCTR
Read/Write
R
R/W
Initial Value
000
0001
0
Table 23-3.
Over-current Protection Reaction Time. OCPT[5:0] with corresponding Over-cur-
rent Delay Time.
Over-current Protection Reaction Time(1) OCPT[5:0]
Typ
0x00
(0.0 - 0.5 ms) + T
0x01
(0.5 - 1.0 ms) + T
0x03
(1.0 - 1.5 ms) + T
...
0x3E
(30.5 - 31.0 ms) + T
d
0x3F
(31.0 - 31.5 ms) + T
d